The present invention relates to a semiconductor integrated circuit on the periphery of which input/output (I/O) circuits and pads, which are interfaces with the outside, are arranged, and more particularly, the invention relates to a semiconductor integrated circuit in which the number of pads is large for the size of the internal circuit.
Conventionally, in a semiconductor integrated circuit, which is a semiconductor chip, a plurality of I/O circuits 1 and pads 2 have been arranged side by side in one row on the periphery outside an internal circuit 3 as shown in FIG. 24.
In recent years, in accordance with the progress in miniaturization of process technology, it becomes possible that more functions than those conventionally achievable are integrated into one semiconductor integrated circuit. The number of I/O circuits placed as interfaces with the outside and the number of pads are increasing. However, the area reduction effect caused by miniaturization differs between low withstand voltage transistors for use in memory circuits, logic circuits, and the like and high withstand voltage transistors for use in analog circuits, I/O circuits, and the like. Compared to memory circuits and logic circuits the areas of which have been significantly reduced by miniaturization of manufacturing processes, analog circuits and I/O circuits have areas that have not significantly been reduced. As a result of such imbalance in area reduction effect, the ratio of the area of analog circuits and I/O circuits to the total area is increasing. For example, as shown in FIG. 25, I/O circuits and pads the numbers of which are determined by the needs of a semiconductor integrated circuit are arranged on the outer periphery of the internal circuit 3 including a memory circuit, a logic circuit, and the like. In this case, an outer peripheral frame formed of the arranged I/O circuits 1 and pads 2 is large compared to the internal circuit 3. As a result, there occurs a wide space between the internal circuit 3 and the I/O circuits and the pads 2. This means occurrence of a waste region. Thus, there has been a drawback that area reduction cannot be achieved although miniaturization progresses in manufacturing processes.
In view of this, conventionally, for example as shown in FIG. 26, there has been proposed a pad arranging method of arranging pads in two rows to achieve good balance between the area of the internal circuit 3 and the area of the outer peripheral frame formed of the arranged I/O circuits 1 and pads 2. With this method, the area of the semiconductor integrated circuit is effectively reduced even though many pads are arranged, as compared to the case of arranging pads in one row. This proposal is disclosed in, e.g., Japanese Unexamined Patent Application Publication No. 9-45723.
In the case where pads are arranged in two rows as mentioned above, the width and height of an I/O circuit for two pads are set in accordance with sizes and arrangement pitches of a plurality of pads to be arranged. In a plurality of I/O circuits arranged on the outer periphery, power source wirings extending in a direction of arrangement of the I/O circuits are formed inside each I/O circuit in order to supply the power to the I/O circuit. When the I/O circuits are arranged neighboring each other, the inside power source wirings are connected to each other such that the connected wirings are typically ring-shaped. Therefore, the I/O circuit for two pads, similarly to the I/O circuit for one pad, is formed in a shape with the width and the height each limited to one kind.
Under such limitation, in the foregoing conventional semiconductor integrated circuit having pads arranged in two rows, pads are arranged in two rows over the entire periphery even when the number of pads required for the semiconductor IC is not so large enough to form two pads in all the sides of the semiconductor integrated circuit. This therefore causes excess pads that are not used for input or output of signals. Such excess pads have conventionally been used to enhance power sources for the purpose of reduction in IR drop, with the power sources assigned to the excess pads.
In the foregoing conventional semiconductor integrated circuit having pads arranged in two rows, the area can be reduced compared to a semiconductor integrated circuit having pads arranged in one row as shown in FIG. 25. However, it has been found that the effect of area reduction is low. For example, in the semiconductor integrated circuit having pads arranged in two rows, if five pads are excessive, the area of the semiconductor integrated circuit is larger than that of a semiconductor integrated circuit without the five excessive pads 2 by the area required for arranging the five excessive pads 2 as indicated by a dotted line in FIG. 26.